ENOSYS project‎ > ‎

Motivation

Today, SoC vendors realize that critical decisions must be made long before development teams engage in the hardware and software design for new SoC and programmable SoC-based products.

It is becoming clear that hardware-software design and verification must form part of a single, unified effort, whereas the methodologies currently available were intended to aid either hardware-only or software-only development. That these tools are no longer adequate for modern SoC designs is confirmed by the recent emergence of new concepts that are disrupting the traditional design flow; these include system-level specification (specification capture), functional and architectural analysis, and high-level estimation, partitioning and software synthesis. While a number of niche tools have been developed to overcome specific deficiencies in the current flow, all too often, time-to-market (TTM) constraints force the adoption of ad hoc solutions in the delivery of commercial SoC designs.

ENOSYS proposes a disruptive approach which will deliver a smooth, well orchestrated flow; one in which the iterations between the central paradigms are minimized, along with the methodology to integrate and balance the intrinsic technologies for the creation of next-generation SoCs. This is achieved using UML-based models, SysML and MARTE, as the entry approaches to produce hybrid (RTL/ESL) VLSI systems.