This page is dedicated to the project news.

ENOSYS Technology Available for Downloading - Free

posted 10 Jan 2013, 08:00 by Alec Vogt   [ updated 10 Jan 2013, 08:14 ]

New capabilities and tool features developed during the ENOSYS project are now available for general access. Free versions of the tools that comprise the core UML to hardware flow have been released as part of activities to enhance the dissemination of project results.

The tools released by ENOSYS partners have been designed to enable users to familiarise themselves with a UML to hardware design methodology. The combination of an appropriate version of the Modelio UML modelling tool and the FalconML Starter Edition behavioral synthesis tool enables the synthesis of UML models to RTL, ready for design implementtaion on FPGAs using a standard EDA tool flow.

The tool can be downloaded from the relevant ENOSYS partner websites.
    Download Modelio (Open Source) from the Modelio website.
    Download FalconML Starter Edition from the Axilica website.

ENOSYS Partners Collaborate to Provide Advanced UML-based Hardware-software Co-design Solutions for Embedded Systems

posted 10 Jan 2013, 07:27 by Alec Vogt   [ updated 10 Jan 2013, 07:36 ]

Axilica and Softeam, through its Modeliosoft division, have signed a collaboration agreement focused on delivering coherent solutions for customers requiring a UML® to hardware and hardware-software co-design methodology.
This collaboration agreement is an extension to the successful relationship already in place between both companies within the ENOSYS project, part of the European Commission’s Seventh Framework Programme for funding and encouraging leading edge research and technological development.  The objectives of the ENOSYS project are to specify and develop a tool flow for designing and implementing embedded systems using the seamless integration of high-level system specifications, software code generation, hardware synthesis and design space exploration.
This agreement enables the commercial exploitation of the technical innovations implemented in ENOSYS for the modelling and synthesis of embedded systems. The Softteam’s Modelio UML modelling tool complemented by Axilica’s FalconML behavioural synthesis tool provide a complete design flow from UML models to RTL (for hardware only design) or RTL and C/C++ (for hardware-software co-design).
The collaboration between Modeliosoft and Axilica will provide solutions to companies developing complex embedded systems, in key market segments such as telecommunications and military aerospace, where the adopting of model-driven methodologies results in reduced time-to-market and product development costs.

ENOSYS Releases First Deliverables for Public Access

posted 30 Jul 2012, 09:46 by Alec Vogt

The ENOSYS Project team has released the first batch of project deliverables for public access. These deliverables are documents and reports that cover a number of topics, from reports of state-of-the-art tools for embedded systems design to detaled descriptions of the ENOSYS flow.

Instructions on how to download these deliverables can be found on the Download page of the ENOSYS project website.

A detailed description of the deliverables that are currently available can be found on the Deliverables page of the ENOSYS website. The deliverables released for public access include:

Deliverable 2.1, State-of-the-Art Analysis for Embedded Systems Design, which records and categorises current embedded systems design practices.

Deliverable 2.2, The ENOSYS Design Flow for the Modelling and Synthesis of Embedded Systems (Preliminary Version), which details the full ENOSYS design flow, from UML design entry all the way to implementation on silicon.

Deliverable 2.3, Methodology for Source Optimization using Transformations, which describes the methodology and implementation of ACOT (Application Code Optimization Tool) developed in the ENOSYS project.

Deliverable 2.4, The Design Space Exploration Methodology, which describes the development of the design space exploration aspects of the ENOSYS project.

Loughborough University Organises ENOSYS Demonstration Day for Industry

posted 31 May 2012, 04:57 by Alec Vogt

Loughborough University, under the auspices of the School of Electronic, Electrical and Systems Engineering, organised on 23 May 2012 at Loughborough (UK) an event dedicated to ENOSYS and the tool flow being developed as part of the project.

The ENOSYS Demonstration Day was organised to present the latest developments in the ENOSYS tools and technology to interested parties in industry.  Loughborough University and Axilica, two of the ENOSYS partners, were joined by representatives from companies based in the UK, operating in a number of market sectors including mil/aero, avionics, EDA (electronic design automation) and semiconductors (FPGA).

The School of Electronic, Electrical and Systems Engineering at Loughborough University undertakes world-leading research in the areas of Electronic System Level Design (ESL) and Multicore/Manycore architectures. In ENOSYS, Loughborough University is developing the design space exploration capabilities and specific tools needed to support the dedicated VLIW multi-core processor (LE1) used in ENOSYS. This event was organised as part of a program at the University to further extend the cooperation between Loughborough University and industry.

A general presentation on the components of the ENOSYS flow was followed by discussions on the benefits that this methodology brings to different industries and future areas of research and collaboration associated with ENOSYS. Two demonstrations, delivered by Loughborough University and Axilica, were used to present project achievements.

The first demonstration covered the core technologies in the ENOSYS flow (UML modelling and behavioural synthesis) using a UML model of an image tracking system for implementation on an Altera® FPGA, first as hardware only and then as a hardware-software system. The demonstration included,

-         Highlighting the benefits of the UML and MARTE subsets used in the ENOSYS language and implemented in the Modelio tool to support model-driven design;

-         Behavioural synthesis using the FalconML tool to provide a C or C++ description of the model for functional simulation and verification; a SystemC description for fast simulation with timing information (TLM models); and, complete RTL description suitable for use in an RTL design flow and ready for a hardware only implementation on an Altera FPGA board;

-         Hardware- software partitioning for codesign at the UML level using MARTE allocations (on the same model used for the hardware only implementation);

-         Behavioural synthesis on the partitioned model to generate C code for software components, RTL for hardware components and the wrappers and communication infrastructure needed to support hardware-software communication;

-         Simulation and validation of the generated components; and

-         Implementation of the complete model on an Altera FPGA with a NIOS® processor.

 The second demonstration focused on the design space exploration capabilities (Jink toolset) developed by Loughborough University. Designed to be driven by properties in the UML model and by user directives, Jink configures and controls all tools in the ENOSYS flow and subsequent implementation flows including the software flow and the RTL to FPGA tool flow. Jink performs the design space exploration validating different system configurations (HW-SW combinations, selection of the number of multi-processor cores) by invoking the relevant tools at each stage of the complete implementation flow. The Jink demonstration showed design space exploration from UML models in Modelio through synthesis in FalconML to achieve HW-SW descriptions and implementation of hardware on an FPGA board alongside software validated in the VLIW multi-core processor (LE1) tool chain.

Trademarks of several owners appear in this news item. The ENOSYS project acknowledges the rights of the respective trademark owners.

ENOSYS White Paper is available in downloads

posted 10 Jan 2012, 07:47 by Andrey Sadovykh

Please check downloads for the new ENOSYS White Paper.

Modelio goes open source, check

posted 4 Oct 2011, 05:25 by Andrey Sadovykh   [ updated 4 Oct 2011, 05:28 ]

http://www.modelio.orgGreat news! Modelio goes open source, check
UML, BPMN enterprise grade modeler with multiple extensions.
MARTE and ENOSYS tools for Modelio are comming to too.

ENOSYS tools demonstration

posted 24 Aug 2011, 05:25 by Andrey Sadovykh

ENOSYS team has released a demonstration presenting an overview of the project results.
In this demo, the tools from SOFTEAM and AXILICA are shown to present a software hardware synthesis of a SoC system.
Modelio by SOFTEAM is used to edit a high-level behavioral model in UML and MARTE.
FalconML by Axilica generates an electronic design for a System-on-Chip.

In overall, the demo presents achievements by the ENOSYS team.

ENOSYS tools demo

New release of MARTE Designer for Modelio

posted 19 Jul 2011, 07:21 by Andrey Sadovykh

Softeam has officially released the MARTE Designer for Modelio.
This add-on is available as an open source at

It is compatible with Modelio Free edition and thus can be used completely free of charge.

This work was co-funded by the European Commission in the frame of the ENOSYS FP7 project.

The ENOSYS Design Flow is Becoming a Reality!

posted 29 Jun 2011, 02:20 by Alec Vogt   [ updated 29 Jun 2011, 02:59 ]

The ENOSYS partners have successfully completed major milestones in the project and have achieved the internal delivery of the first version of the ENOSYS design flow.


Work in the project has focused on consolidating the methodology and infrastructure needed to implement the full ENOSYS design flow for the HW/SW co-design of embedded systems.  The proactive collaboration between project partners has delivered key technical contributions, which have been incorporated into various stages of the design flow.  These include,
  • A draft definition of the ENOSYS Language which was used to define new capabilities needed in the modelling and behavioural synthesis tools that are part of the design flow. The ENOSYS language is a language for the representation of hardware/software systems, based on a subset of UML. Individual actions in the UML model are written in a C subset and the UML MARTE profile is used to annotate non-functional properties, such as time or resource utilisation, into the model. In addition, the project team has identified and included in the ENOSYS language some representations used in the design flow are unique to the ENOSYS flow and which are essential to the efficient modelling and implementation of embedded systems;
  • Extended support for action languages in UML to include C and new capabilities for C++ based on feedback from the industrial partners;
  • A number of enhancements that have been implemented in the modelling and behavioural synthesis stages of the flow to meet the stringent requirements of the industrial test cases;
  •  The definition of the architecture for the main target FPGA platform to be used to develop the overall ENOSYS design flow, which will include:
    • The LE1 - a parameterisable VLIW multi-processor;
    • Hardware synthesised through the ENOSYS flow; and
    • A MicroBlaze™ processor and PLB interconnect (available as part of the selected Xilinx® FPGA);
  • A demonstration of the capabilities of the LE1 was posted on our project website, ; and
  • Further development of the design space exploration and source code optimisation tools to consolidate links between these tools and other tools in the design flow. The team also completed the first demonstrations of the complete flow under control of design space exploration,

Delivery of the first version of the ENOSYS design flow will be followed by extensive testing of the flow against requirements to be undertaken by the ENOSYS industrial partners. This first version of the design flow has already had a commercial impact with the project SME partners releasing software products that incorporate enhancements developed partly through ENOSYS:

·        Softeam has released an alpha version of its MARTE open source modules for its Modelio product which is UML modelling tool for the ENOSYS design flow (see; and

ENOSYS 1st Annual review - non official results

posted 11 Mar 2011, 06:31 by Andrey Sadovykh   [ updated 11 Mar 2011, 06:38 ]

The first annual review of the ENOSYS project was held on 10th March 2011.
The project progress was assessed by a independent industry experts.

The first feedbacks after the review by the European Commission and the experts are extremely positive.
The consortium showed great cooperation and excellent scientific results in the first year.
The project is totally on track towards the objectives.

More results will follow in the year 2.

The ENOSYS public deliverables will be soon uploaded to the web-site after official reports by the experts.

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