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ENOSYS presentation at DATE 2012

News

This page is dedicated to the project news.

ENOSYS White Paper is available in downloads

posted 10 Jan 2012 07:47 by Andrey Sadovykh

Please check downloads for the new ENOSYS White Paper.

Modelio goes open source, check http://www.modelio.org

posted 4 Oct 2011 05:25 by Andrey Sadovykh   [ updated 4 Oct 2011 05:28 ]

http://www.modelio.orgGreat news! Modelio goes open source, check http://www.modelio.org
UML, BPMN enterprise grade modeler with multiple extensions.
.
MARTE and ENOSYS tools for Modelio are comming to forge.modelio.org too.

ENOSYS tools demonstration

posted 24 Aug 2011 05:25 by Andrey Sadovykh

ENOSYS team has released a demonstration presenting an overview of the project results.
In this demo, the tools from SOFTEAM and AXILICA are shown to present a software hardware synthesis of a SoC system.
Modelio by SOFTEAM is used to edit a high-level behavioral model in UML and MARTE.
FalconML by Axilica generates an electronic design for a System-on-Chip.

In overall, the demo presents achievements by the ENOSYS team.

ENOSYS tools demo





New release of MARTE Designer for Modelio

posted 19 Jul 2011 07:21 by Andrey Sadovykh

Softeam has officially released the MARTE Designer for Modelio.
This add-on is available as an open source at http://sourceforge.net/projects/modelio-open/files/MARTEDesigner/

It is compatible with Modelio Free edition and thus can be used completely free of charge.

This work was co-funded by the European Commission in the frame of the ENOSYS FP7 project.

The ENOSYS Design Flow is Becoming a Reality!

posted 29 Jun 2011 02:20 by Alec Vogt   [ updated 29 Jun 2011 02:59 ]

The ENOSYS partners have successfully completed major milestones in the project and have achieved the internal delivery of the first version of the ENOSYS design flow.

 

Work in the project has focused on consolidating the methodology and infrastructure needed to implement the full ENOSYS design flow for the HW/SW co-design of embedded systems.  The proactive collaboration between project partners has delivered key technical contributions, which have been incorporated into various stages of the design flow.  These include,
  • A draft definition of the ENOSYS Language which was used to define new capabilities needed in the modelling and behavioural synthesis tools that are part of the design flow. The ENOSYS language is a language for the representation of hardware/software systems, based on a subset of UML. Individual actions in the UML model are written in a C subset and the UML MARTE profile is used to annotate non-functional properties, such as time or resource utilisation, into the model. In addition, the project team has identified and included in the ENOSYS language some representations used in the design flow are unique to the ENOSYS flow and which are essential to the efficient modelling and implementation of embedded systems;
  • Extended support for action languages in UML to include C and new capabilities for C++ based on feedback from the industrial partners;
  • A number of enhancements that have been implemented in the modelling and behavioural synthesis stages of the flow to meet the stringent requirements of the industrial test cases;
  •  The definition of the architecture for the main target FPGA platform to be used to develop the overall ENOSYS design flow, which will include:
    • The LE1 - a parameterisable VLIW multi-processor;
    • Hardware synthesised through the ENOSYS flow; and
    • A MicroBlaze™ processor and PLB interconnect (available as part of the selected Xilinx® FPGA);
  • A demonstration of the capabilities of the LE1 was posted on our project website, http://www.enosys-project.eu/ ; and
  • Further development of the design space exploration and source code optimisation tools to consolidate links between these tools and other tools in the design flow. The team also completed the first demonstrations of the complete flow under control of design space exploration,

Delivery of the first version of the ENOSYS design flow will be followed by extensive testing of the flow against requirements to be undertaken by the ENOSYS industrial partners. This first version of the design flow has already had a commercial impact with the project SME partners releasing software products that incorporate enhancements developed partly through ENOSYS:

·        Softeam has released an alpha version of its MARTE open source modules for its Modelio product which is UML modelling tool for the ENOSYS design flow (see http://rd.softeam.com/prototypes); and

ENOSYS 1st Annual review - non official results

posted 11 Mar 2011 06:31 by Andrey Sadovykh   [ updated 11 Mar 2011 06:38 ]

The first annual review of the ENOSYS project was held on 10th March 2011.
The project progress was assessed by a independent industry experts.

The first feedbacks after the review by the European Commission and the experts are extremely positive.
The consortium showed great cooperation and excellent scientific results in the first year.
The project is totally on track towards the objectives.

More results will follow in the year 2.

The ENOSYS public deliverables will be soon uploaded to the web-site after official reports by the experts.

ENOSYS: LE1 & Microblaze Demo by Loughborough University

posted 7 Mar 2011 05:43 by Andrey Sadovykh




M12 Plenary meeting

posted 8 Feb 2011 06:59 by Andrey Sadovykh

The M12 plenary meeting was held in Paris in SOFTEAM premises.

Among the project management issues, partners held a technical collocation and  reviewed the status of the tools development.

The major topics were:
- ENOSYS language,
- Synthesis in C,
- progress with automated partitioning,
- LE1 development progress and
- source code optimization

Best wishes for the holidays and 2011 !

posted 24 Dec 2010 05:37 by Andrey Sadovykh   [ updated 24 Dec 2010 05:38 ]


SOFTEAM has officially entered the MARTE revision task force

posted 24 Dec 2010 05:22 by Andrey Sadovykh

SOFTEAM has entered the MARTE revision task force and intends to promote the ENOSYS project results in OMG

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