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Loughborough University Organises ENOSYS Demonstration Day for Industry

posted 31 May 2012, 04:57 by Alec Vogt

Loughborough University, under the auspices of the School of Electronic, Electrical and Systems Engineering, organised on 23 May 2012 at Loughborough (UK) an event dedicated to ENOSYS and the tool flow being developed as part of the project.

The ENOSYS Demonstration Day was organised to present the latest developments in the ENOSYS tools and technology to interested parties in industry.  Loughborough University and Axilica, two of the ENOSYS partners, were joined by representatives from companies based in the UK, operating in a number of market sectors including mil/aero, avionics, EDA (electronic design automation) and semiconductors (FPGA).

The School of Electronic, Electrical and Systems Engineering at Loughborough University undertakes world-leading research in the areas of Electronic System Level Design (ESL) and Multicore/Manycore architectures. In ENOSYS, Loughborough University is developing the design space exploration capabilities and specific tools needed to support the dedicated VLIW multi-core processor (LE1) used in ENOSYS. This event was organised as part of a program at the University to further extend the cooperation between Loughborough University and industry.

A general presentation on the components of the ENOSYS flow was followed by discussions on the benefits that this methodology brings to different industries and future areas of research and collaboration associated with ENOSYS. Two demonstrations, delivered by Loughborough University and Axilica, were used to present project achievements.

The first demonstration covered the core technologies in the ENOSYS flow (UML modelling and behavioural synthesis) using a UML model of an image tracking system for implementation on an Altera® FPGA, first as hardware only and then as a hardware-software system. The demonstration included,

-         Highlighting the benefits of the UML and MARTE subsets used in the ENOSYS language and implemented in the Modelio tool to support model-driven design;

-         Behavioural synthesis using the FalconML tool to provide a C or C++ description of the model for functional simulation and verification; a SystemC description for fast simulation with timing information (TLM models); and, complete RTL description suitable for use in an RTL design flow and ready for a hardware only implementation on an Altera FPGA board;

-         Hardware- software partitioning for codesign at the UML level using MARTE allocations (on the same model used for the hardware only implementation);

-         Behavioural synthesis on the partitioned model to generate C code for software components, RTL for hardware components and the wrappers and communication infrastructure needed to support hardware-software communication;

-         Simulation and validation of the generated components; and

-         Implementation of the complete model on an Altera FPGA with a NIOS® processor.

 The second demonstration focused on the design space exploration capabilities (Jink toolset) developed by Loughborough University. Designed to be driven by properties in the UML model and by user directives, Jink configures and controls all tools in the ENOSYS flow and subsequent implementation flows including the software flow and the RTL to FPGA tool flow. Jink performs the design space exploration validating different system configurations (HW-SW combinations, selection of the number of multi-processor cores) by invoking the relevant tools at each stage of the complete implementation flow. The Jink demonstration showed design space exploration from UML models in Modelio through synthesis in FalconML to achieve HW-SW descriptions and implementation of hardware on an FPGA board alongside software validated in the VLIW multi-core processor (LE1) tool chain.

Trademarks of several owners appear in this news item. The ENOSYS project acknowledges the rights of the respective trademark owners.

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