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The ENOSYS Design Flow is Becoming a Reality!

posted 29 Jun 2011, 02:20 by Alec Vogt   [ updated 29 Jun 2011, 02:59 ]

The ENOSYS partners have successfully completed major milestones in the project and have achieved the internal delivery of the first version of the ENOSYS design flow.


Work in the project has focused on consolidating the methodology and infrastructure needed to implement the full ENOSYS design flow for the HW/SW co-design of embedded systems.  The proactive collaboration between project partners has delivered key technical contributions, which have been incorporated into various stages of the design flow.  These include,
  • A draft definition of the ENOSYS Language which was used to define new capabilities needed in the modelling and behavioural synthesis tools that are part of the design flow. The ENOSYS language is a language for the representation of hardware/software systems, based on a subset of UML. Individual actions in the UML model are written in a C subset and the UML MARTE profile is used to annotate non-functional properties, such as time or resource utilisation, into the model. In addition, the project team has identified and included in the ENOSYS language some representations used in the design flow are unique to the ENOSYS flow and which are essential to the efficient modelling and implementation of embedded systems;
  • Extended support for action languages in UML to include C and new capabilities for C++ based on feedback from the industrial partners;
  • A number of enhancements that have been implemented in the modelling and behavioural synthesis stages of the flow to meet the stringent requirements of the industrial test cases;
  •  The definition of the architecture for the main target FPGA platform to be used to develop the overall ENOSYS design flow, which will include:
    • The LE1 - a parameterisable VLIW multi-processor;
    • Hardware synthesised through the ENOSYS flow; and
    • A MicroBlaze™ processor and PLB interconnect (available as part of the selected Xilinx® FPGA);
  • A demonstration of the capabilities of the LE1 was posted on our project website, ; and
  • Further development of the design space exploration and source code optimisation tools to consolidate links between these tools and other tools in the design flow. The team also completed the first demonstrations of the complete flow under control of design space exploration,

Delivery of the first version of the ENOSYS design flow will be followed by extensive testing of the flow against requirements to be undertaken by the ENOSYS industrial partners. This first version of the design flow has already had a commercial impact with the project SME partners releasing software products that incorporate enhancements developed partly through ENOSYS:

·        Softeam has released an alpha version of its MARTE open source modules for its Modelio product which is UML modelling tool for the ENOSYS design flow (see; and